Present day digital circuit applications often involve analog-to-digital data converters (ADCs), which includes sampling circuitry that samples an analog input signal at points in time, and then converts the samples to digital values to create a digital signal. The use of ADCs is common for certain types of applications, which can involve receiving an input signal or input data represented by an analog signal, and then converting the analog signal to a digital signal for further processing by a logic block in a digital form. To provide the samples to the logic block, a serialized interface according to a format is often used. Specifically, data samples are organized as frames according to the serialized interface, and the frames are transmitted serially over one or more lanes to a logic block. In one example, a transmitter is provided with a framer which interfaces between (analog-to-digital) data converters and a logic block.
One example of a serialized interface is the JESD204x series of standards which defines a serialized interface between data converters and logic devices, written by the JEDEC Solid State Technology Association. For instance, the JESDC Solid State Technology Association has written a JESD204A standard in April 2008, and a JESD204B standard in July 2011. The JESD204B standard in particular defines a large range of possible specifications for a serial link (e.g., having different number of data converters, sample resolutions, and number of lanes). Furthermore, the standard defines a framing protocol for a range of specifications having different frame sizes and samples per frame.
Each application may have a different specification, where a particular specification may include a particular number of data converters, a particular number of links available for the logic block, a particular number of bits per converter, a particular number of samples per converter per frame, etc. Depending on the application, a designer would design circuits for the framer specific to the specification. The design process is time consuming and difficult. Moreover, the designer should have an in depth knowledge of the serialized interface and the format that the interface uses to design a suitable circuit.
Overview
The disclosure relates generally to a framer supporting a serial interface standard for data converters defined by the JEDEC Solid State Technology Association. Generally, the framer may be used in high speed (e.g., 8 Gb/s, 12.5 Gb/s or higher) analog-to-digital converter applications.
Framer
The present disclosure relates generally to a framer for interfacing between one or more data converters and a logic device, wherein the synthesis of hardware for the framer is defined by one or more parameters. In other words, the hardware can be synthesized to support different specifications defined by the parameters. Furthermore, by using different values for the parameters, the synthesized hardware may result in varying logic gates and circuits having different characteristics such as size, area, and/or power consumption.
In the context of this disclosure, it is noted that the one or more parameters may be defined in a register transfer level (RTL) description using a hardware description language (HDL) such as Verilog or VHSIC Hardware Description Language (VHDL). The synthesis of hardware defined by one or more parameters may occur in different ways. In a first instance, the hardware, i.e., a chip such as a Field Programmable Gate Array (FPGA) already exists. The RTL description includes the one or more parameters. The FPGA is then configured (i.e., through logic synthesis) according to the RTL description. The one or more parameters would dictate how much of the FPGA is utilized and how the FPGA should be synthesized/configured. In a second instance, the hardware has not been built or generated yet. A fabrication entity receives the RTL description which includes the one or more parameters. Based on the RTL description, an application-specific integrated circuit (ASIC) is built/generated, e.g., synthesized using templates or designs for basic building blocks. The one or more parameters would dictate how much hardware is generated.
One of the many advantages of such a parameterizable framer obviates the need for a designer to implement the framer from scratch. The parameters, e.g., hardware instance parameters, may include at least one of: a total number of bits per converter, a number of lane(s), and a size of an input bus for providing the one or more samples from the one or more data converters. Based on the one or more parameters, the framer is configured to support a specification defined by at least one of: a number of data converter(s), a number of sample(s) per converter, the total number of bits per converter, the number of lane(s), and a frame size. The framer may be configured to support more than one specification, where one specification may be selected as the active configuration through software configuration.
The framer comprises a transport layer and a data link layer. The transport layer configured to map one or more samples from the one or more data converters into one or more frames in a frame memory. The data link layer configured to provide the one or more frames over one or more lanes to a logic device according to a serialized interface. The transport layer provides the key mechanism for mapping samples to frames and frames to lanes. Each lane is then processed by the data link layer to provide frames over the lanes according to the serialized interface.
A parameterizable framer allows a designer to instantiate/synthesize hardware for a framer based on a set of instance parameters, and further configure the framer through software configuration. The architecture provided by the framer enables flexibility in using the framer for a large variety of applications without having to waste resources in designing a specific framer for the specific application. Advantageously, the active specification of the framer can be changed from one to another though software configuration to further increase flexibility of the synthesized hardware.
In one embodiment, the framer is further software configurable via one or more input signals to the framer to change the active specification for at least one of: the total number of bits per converter, the number of data converter(s), the number of sample(s) per converter, and the number of lane(s). Software configurability provides the option for using the framer under different modes (i.e., different link configurations/specifications) within the synthesized hardware provided by the instance parameters
In one embodiment, the framer is a quad-byte framer configured to process four octets in parallel. The framer thus outputs four consecutive 10-bit encoded symbols per lane to the logic device in one clock cycle. The framer operates at a clock rate that is 1/40 of the serial link rate of the one or more lanes. The reduction of the clock rate is particularly useful for configuring the framer on programmable hardware which runs at a relatively slower clock rate while achieving comparable data link rates.
In one embodiment, the one or more parameters further include a first alternate number of bits per converter. The framer is software configurable via an input signal adapted to select one of the total number of bits per converter, and the first alternate number of bits per converter, for use as the active specification of the framer. Such a framer may support multiple (link) specifications within the synthesized hardware, and a selector input may be used advantageously (i.e., via software configuration) to select which mode or active specification the framer should operate.
In one embodiment, one or more multiplexers between the transport layer and the data link layer, the one or more multiplexers adapted to provide the one or more frames in the lower numbered lane(s) if the frame size is increased to a value 8 or greater. The multiplexers advantageously provide the means to conveniently parse the frames to the lower contiguous lanes when the number of active lanes can be reduced (e.g., when the frames in frame memory can be parsed onto fewer active lanes due to an increase in frame size).
A method for providing a framer suitable for interfacing between one or more data converters and a logic device based on one or more parameters is disclosed. One or more non-transitory tangible media that includes code for execution and when executed by a processor is operable to perform operations to provide a framer through synthesis is also disclosed. The method and the code are related to steps for providing the hardware for the framer through synthesis in accordance with the parameters.
Transport Layer Test Sequence Generator
The present disclosure also relates to an apparatus for verifying the compliance of a framer, wherein the framer is configured to interface between one or more data converters and a logic device and to provide a plurality of frames to the logic device according to a serialized interface. The present disclosure also relates to the synthesis of the apparatus. The apparatus includes a transport layer test sequence generator, and the synthesis of the transport layer test sequence generator is parameterizable through one or more parameters. The transport layer test sequence generator is configured to support a specification used by the framer.
The transport layer test sequence generator adapted to replace one or more samples from the one or more data converters with a transport layer test sequence. The transport layer test sequence generator may be synthesized based on a specification of the framer including at least one of: a number of bits per converter, a number of data converter(s), and a number of sample(s) per converter per frame. The transport layer test sequence comprises at least one of: one or more converter identifiers, one or more sample identifiers, and a shifted pattern of control bits over the plurality of frames. Advantageously, the synthesis of the transport layer test sequence generator is parameterizable to match the specification supported by the framer for which the test sequence generator is used. This obviates the need for a designer to hardcode the test sequence for a particular application or to design custom circuits from scratch.
The transport layer test sequence generator comprises a converter identifier generator, a sample identifier generator, and a control bit shifter. These components may be synthesized based on the parameters used for synthesizing the framer. The converter identifier generator and the sample identifier generator each comprises an adder tree. The number of adders in the adder tree is parameterizable based on, e.g., the size of the input bus for providing the data samples to the transport layer. The control bit shifter comprises a shift register and the length of the shift register is parameterizable based on the size of the input bus. A map is provided which puts together the outputs from these components into a transport layer test sequence according to the specification(s) supported by the framer. In one instance, the transport layer test sequence comprises the Long Test Sequence defined in the JESD204B Standard by the JEDEC Solid State Technology Association.
A method for providing an apparatus for verifying the compliance of a framer is disclosed. One or more non-transitory tangible media that includes code for execution and when executed by a processor is operable to perform operations to provide an apparatus for verifying the compliance of a framer, is also disclosed. The method and the code are related to steps for providing the hardware for the apparatus through synthesis in accordance with the parameters.